#ifndef __RADAR_DEF_H__
#define __RADAR_DEF_H__

#include <stdint.h>
#include "sdk_ifs_udk_cfg.h"
#include "udk_default_def.h"
//#include "GPIO_Driver.h"
//#include "udp_def.h"

// ***start 下述宏定义值修改，请在radar_user_pre_def.h中修改，不要修改本文件
#if !defined(CFAR_MAX_NUM)
#define CFAR_MAX_NUM (128)
#endif

#if !defined(PCRST_MAX)
#define PCRST_MAX    (128)
#define FRAME_MAX_NUM PCRST_MAX
#endif

#if !defined(ALPHA_FILTER_NUM_MAX)
#define ALPHA_FILTER_NUM_MAX (10)
#endif

#if !defined(CLUSTER_NUM_MAX)
#define CLUSTER_NUM_MAX (20)
#endif

#if !defined(RADAR_EPC_NUM_MAX)
#define RADAR_EPC_NUM_MAX (32)
#endif
// ***end

#define CFAR1_EN   (0)
#define CFAR2_EN   (1)
#define CFAR12_EN  (2)

/* pc_rst */
typedef struct {
	STRUCT_POINTRST_DEF;
	STRUCT_TARGETPOINT target_buff[PCRST_MAX];
}pc_rst_t;

/* epc */
typedef struct{
	STRUCT_EPC_DEF;
	struct epc_target target_buff[RADAR_EPC_NUM_MAX];
}epc_t;

#define MAX_APP_DATA (254)
struct app_protocol{
	uint8_t app_id;
	uint8_t app_len;
	uint8_t app_data[MAX_APP_DATA];
};

/* alpha 滤波*/
typedef struct{
	ALPHA_FILTER_DEF;
	struct alpha_target target[ALPHA_FILTER_NUM_MAX];
	struct alpha_target_ordered ordered_temp[ALPHA_FILTER_NUM_MAX];
}alpha_filter_t;

/*dbscan 聚类*/

#define CLUSTER_INPUT_MAX (PCRST_MAX)

typedef struct{
	struct // input
	{
		DBSCANFRAME_DEF;
		DBSCANPT pt_buff[CLUSTER_INPUT_MAX];
	}dbscan_frame;
	
	struct // output
	{
		DBSCANOUT_DEF;
		clusterRpt cluster_buff[CLUSTER_NUM_MAX];
	}dbscanClu;
	struct // nb-a
	{
		DBSCANNB_DEF;
		uint8_t idx_buff[CLUSTER_INPUT_MAX];
	}dbscan_nbA;
	struct // nb-b
	{
		DBSCANNB_DEF;
		uint8_t idx_buff[CLUSTER_INPUT_MAX];
	}dbscan_nbB;
	
	DBSCANCFG    dbscan_cfg;
}dbscan_cluster_t;


/*
* BBE相关
*/
#define GET_ADDRESS(offset) (offset|(BBE_ABUF_BASE&0xF0000000))
#define GET_OFFSET(addr) (addr&0x0FFFFFFF)


/* 预定义 */
#if 1
#define ANA1_CFG0_DEFAULT (0x000000C0)
#define ANA1_CFG1_DEFAULT (0x18300000)
#define ANA1_CFG2_DEFAULT (0x58108A00)
	
#define ANA2_CFG0_DEFAULT (0x000000C0)
#define ANA2_CFG1_DEFAULT (0x10000040)
#define ANA2_CFG2_DEFAULT (0xF080AB00)
	
#define ANA3_CFG0_DEFAULT (0x000000C0)
#define ANA3_CFG1_DEFAULT (0x10000040)
#define ANA3_CFG2_DEFAULT (0xF080AB00)

#define ANA4_CFG0_DEFAULT (0x000000C0)
#define ANA4_CFG1_DEFAULT (0x18300000)
#define ANA4_CFG2_DEFAULT (0x58108A00)

#define UDP_CFG_RAMP_WAVE0_WAVE1_ONCE ( 0x00003101 )
#define UDP_CFG_RAMP_WAVE0_WAVE1_INF  ( 0x00003100 )
#define UDP_CFG_RAMP_WAVE0_INF        ( 0x00003000 )

#define UDP_CFG_RAMP_PLL_23G      ( 0x00FC0000 )
#define UDP_CFG_RAMP_PLL_23G2     ( 0x01100000 )
#define UDP_CFG_RAMP_PLL_23G4     ( 0x01240000 )
#define UDP_CFG_RAMP_PLL_23G5     ( 0x012E0000 )
#define UDP_CFG_RAMP_PLL_23G6     ( 0x01380000 )
#define UDP_CFG_RAMP_PLL_23G7     ( 0x01420000 )
#define UDP_CFG_RAMP_PLL_24G01    ( 0x01610000 )
#define UDP_CFG_RAMP_PLL_24G      ( 0x01600000 )


/* 20Mhz */

#define XTAL20M_RAMP_0G_1US       ( 0x00000008 )
#define XTAL20M_RAMP_0G_10US      ( 0x00000064 )
#define XTAL20M_RAMP_0G1_10US     ( 0x03330064 )
#define XTAL20M_RAMP_0G1_496US    ( 0x00101360 )
#define XTAL20M_RAMP_0G1_540US    ( 0x000F1518 )
#define XTAL20M_RAMP_0G1_246US    ( 0x0021099C )
#define XTAL20M_RAMP_0G1_261US    ( 0x001F0A30 )
#define XTAL20M_RAMP_0G1_1400US   ( 0x000536B0 )
#define XTAL20M_RAMP_0G1_3000US   ( 0x00027530 )
#define XTAL20M_RAMP_0G1_10US_M   ( 0x80000000 | XTAL20M_RAMP_0G1_10US )

#define XTAL20M_RAMP_0G23_17US    ( 0x046100A8 )
#define XTAL20M_RAMP_0G23_30US    ( 0x0274012C )
#define XTAL20M_RAMP_0G23_30US_M  ( 0x80000000 | XTAL20M_RAMP_0G23_30US )

#define XTAL20M_RAMP_0G22_17US    ( 0x043000A8 )
#define XTAL20M_RAMP_0G22_30US    ( 0x0258012C )
#define XTAL20M_RAMP_0G22_30US_M  ( 0x80000000 | XTAL20M_RAMP_0G22_30US )

#define XTAL20M_RAMP_0G25_34US    ( 0x025A0154 ) // 0.25G 34us
#define XTAL20M_RAMP_0G25_30US    ( 0x02AA012C ) // 0.25G 30us
#define XTAL20M_RAMP_0G25_30US_M  ( 0x80000000 | XTAL20M_RAMP_0G25_30US )    // -0.25G 30us


#define XTAL20M_RAMP_0G8_110US    ( 0x0253044C ) // 0.8G 110us
#define XTAL20M_RAMP_0G8_30US     ( 0x0888012C ) // 0.8G 30us
#define XTAL20M_RAMP_0G8_60US     ( 0x04440258 ) // 0.8G 60us
#define XTAL20M_RAMP_0G8_30US_M   ( 0x80000000 | XTAL20M_RAMP_0G8_30US )     // -0.25G 30us

#define XTAL20M_RAMP_1G6_120US    ( 0x044404B0 ) //  1.6G 120us
#define XTAL20M_RAMP_1G6_110US    ( 0x04A7044C ) //  1.6G 110us
#define XTAL20M_RAMP_1G6_60US     ( 0x08880258 ) //  1.6G 60us
#define XTAL20M_RAMP_1G6_30US     ( 0x1111012C ) //  1.6G 30us
#define XTAL20M_RAMP_1G6_30US_M   ( 0x80000000 | XTAL20M_RAMP_1G6_30US )    // -1.6G 30us

/* 40Mhz */

#define XTAL40M_RAMP_0G_1US       ( 0x00000014 )
#define XTAL40M_RAMP_0G_5US       ( 0x00000064 )
#define XTAL40M_RAMP_0G_7US       ( 0x0000008c )
#define XTAL40M_RAMP_0G_10US      ( 0x000000C8 )
#define XTAL40M_RAMP_0G_440US     ( 0x00002260 )
#define XTAL40M_RAMP_0G_100US     ( 0x000007D0 )
//#define XTAL40M_RAMP_0G_40US      ( 0x00000320 )

#define XTAL40M_RAMP_0G1_3000US   ( 0x0001EA60 )
#define XTAL40M_RAMP_0G1_1400US   ( 0x00026D60 )
#define XTAL40M_RAMP_0G1_540US    ( 0x00072A30 )
#define XTAL40M_RAMP_0G1_470US    ( 0x000824B8 )

#define XTAL40M_RAMP_0G1_396US    ( 0x000A1EF0 )
#define XTAL40M_RAMP_0G1_266US    ( 0x000F14C8 )
#define XTAL40M_RAMP_0G1_261US    ( 0x000F1464 )

#define XTAL40M_RAMP_0G1_146US    ( 0x001C0B68 )
#define XTAL40M_RAMP_0G1_346US    ( 0x000B1B08 )
#define XTAL40M_RAMP_0G1_446US    ( 0x000922D8 )

#define XTAL40M_RAMP_0G1_166US    ( 0x00180CF8 )
#define XTAL40M_RAMP_0G1_366US    ( 0x000B1C98 )
#define XTAL40M_RAMP_0G1_466US    ( 0x00082468 )
#define XTAL40M_RAMP_0G1_516US    ( 0x00072850 )

#define XTAL40M_RAMP_0G1_170US    ( 0x00180D48 )
#define XTAL40M_RAMP_0G1_358US    ( 0x000B1BF8 )
#define XTAL40M_RAMP_0G1_452US    ( 0x00092350 )
#define XTAL40M_RAMP_0G1_499US    ( 0x000826FC )

//#define XTAL40M_RAMP_0G1_490US    ( 0x00082648 )
#define XTAL40M_RAMP_0G1_246US    ( 0x00101338 )
#define XTAL40M_RAMP_0G1_496US    ( 0x000826C0 )
#define XTAL40M_RAMP_0G1_100US    ( 0x002807D0 )
#define XTAL40M_RAMP_0G1_10US     ( 0x019900C8 )
#define XTAL40M_RAMP_0G1_20US     ( 0x00CC0190 )
#define XTAL40M_RAMP_0G1_40US     ( 0x00660320 )
#define XTAL40M_RAMP_0G1_10US_M   ( 0x80000000 | XTAL40M_RAMP_0G1_10US )

#define XTAL40M_RAMP_0G1_890US    ( 0x00044588 )
#define XTAL40M_RAMP_0G1_1890US   ( 0x000293A8 )
#define XTAL40M_RAMP_0G1_2890US   ( 0x0001E1C8 )

#define XTAL40M_RAMP_0G092_10US   ( 0x017800C8 )
#define XTAL40M_RAMP_0G092_10US_M ( 0x80000000 | XTAL40M_RAMP_0G092_10US )

#define XTAL40M_RAMP_0G093_10US   ( 0x017C00C8 )
#define XTAL40M_RAMP_0G093_10US_M ( 0x80000000 | XTAL40M_RAMP_0G093_10US )


#define XTAL40M_RAMP_0G22_110US   ( 0x00510898 )	
#define XTAL40M_RAMP_0G22_30US    ( 0x012C0258 )
#define XTAL40M_RAMP_0G22_40US    ( 0x00E10320 )
#define XTAL40M_RAMP_0G22_40US_M  ( 0x80000000 | XTAL40M_RAMP_0G22_40US )
#define XTAL40M_RAMP_0G22_30US_M  ( 0x80000000 | XTAL40M_RAMP_0G22_30US )
#define XTAL40M_RAMP_0G22_55US    ( 0x00A3044C )

#define XTAL40M_RAMP_0G22_830US   ( 0x000A40D8 ) // 0.22G 830us
#define XTAL40M_RAMP_0G22_860US   ( 0x000A4330 ) // 0.22G 860us
#define XTAL40M_RAMP_0G22_960US   ( 0x00094B00 ) // 0.22G 960us
#define XTAL40M_RAMP_0G22_440US   ( 0x00142260 ) // 0.22G 440us
#define XTAL40M_RAMP_0G22_220US   ( 0x00281130 ) // 0.22G 220us

#define XTAL40M_RAMP_0G22_17US    ( 0x02120154 ) // 0.22G 17us
#define XTAL40M_RAMP_0G22_15US    ( 0x0258012C ) // 0.22G 15us
#define XTAL40M_RAMP_0G22_15US_M  ( 0x80000000 | XTAL40M_RAMP_0G22_15US )   // -0.22G 15us


#define XTAL40M_RAMP_0G22_20US    ( 0x01C20190 )
#define XTAL40M_RAMP_0G22_20US_M  ( 0x80000000 | XTAL40M_RAMP_0G22_20US )

#define XTAL40M_RAMP_0G23_17US    ( 0x022A0154 )
#define XTAL40M_RAMP_0G23_30US    ( 0x013A0258 )
#define XTAL40M_RAMP_0G23_30US_M  ( 0x80000000 | XTAL40M_RAMP_0G23_30US )

#define XTAL40M_RAMP_0G23_20US    ( 0x01D70190 )
#define XTAL40M_RAMP_0G23_20US_M  ( 0x80000000 | XTAL40M_RAMP_0G23_20US )

#define XTAL40M_RAMP_0G23_60US    ( 0x009D04b0 )
#define XTAL40M_RAMP_0G23_53US    ( 0x00B10424 )
#define XTAL40M_RAMP_0G23_28US    ( 0x01500230 )
#define XTAL40M_RAMP_0G25_7US     ( 0x05B6008C ) // 0.25G   7us
#define XTAL40M_RAMP_0G25_10US    ( 0x040000C8 ) // 0.25G  10us
#define XTAL40M_RAMP_0G25_17US    ( 0x025A0154 ) // 0.25G  17us

#define XTAL40M_RAMP_0G25_55US     ( 0x00BA044C ) // 0.25G  55us
#define XTAL40M_RAMP_0G25_60US     ( 0x00AA04B0 ) // 0.25G  60us
#define XTAL40M_RAMP_0G25_110US    ( 0x005D0898 ) // 0.25G  110us

#define XTAL40M_RAMP_0G25_112US    ( 0x005B08C0 ) // 0.25G  112us
#define XTAL40M_RAMP_0G25_115US    ( 0x005908FC ) // 0.25G  115us

#define XTAL40M_RAMP_0G25_2000US   ( 0x00059C40 ) // 0.25G 2000us
#define XTAL40M_RAMP_0G25_2000US_M ( 0x80000000 | XTAL40M_RAMP_0G25_2000US ) // -0.25G 2000us
#define XTAL40M_RAMP_0G25_475US    ( 0x0015251C ) // 0.25G 475us
#define XTAL40M_RAMP_0G25_475US_M  ( 0x80000000 | XTAL40M_RAMP_0G25_475US )  // -0.25G 475us

#define XTAL40M_RAMP_0G25_34US    ( 0x012D02A8 ) // 0.25G 34us
#define XTAL40M_RAMP_0G25_30US    ( 0x01550258 ) // 0.25G 30us
#define XTAL40M_RAMP_0G25_30US_M  ( 0x80000000 | XTAL40M_RAMP_0G25_30US )    // -0.25G 30us

#define XTAL40M_RAMP_0G8_110US    ( 0x01290898 ) //  0.8G 110us
#define XTAL40M_RAMP_0G8_55US     ( 0x0253044C ) //  0.8G 55us
#define XTAL40M_RAMP_0G8_60US     ( 0x022204B0 ) //  0.8G 60us
#define XTAL40M_RAMP_0G8_30US     ( 0x04440258 ) //  0.8G 30us
#define XTAL40M_RAMP_0G8_30US_M   ( 0x80000000 | XTAL40M_RAMP_0G8_30US )    // -0.8G 30us
#define XTAL40M_RAMP_0G8_5US      ( 0x19990064 ) //  0.8G 5us
#define XTAL40M_RAMP_0G8_5US_M    ( 0x80000000 | XTAL40M_RAMP_0G8_5US )

#define XTAL40M_RAMP_0G8_920US    ( 0x002347e0 )
#define XTAL40M_RAMP_0G8_920US_M  ( 0x80000000 | XTAL40M_RAMP_0G8_920US )

#define XTAL40M_RAMP_0G8_1920US   ( 0x00119600 )
#define XTAL40M_RAMP_0G8_1920US_M ( 0x80000000 | XTAL40M_RAMP_0G8_1920US )

#define XTAL40M_RAMP_1G6_120US    ( 0x02220960 ) //  1.6G 120us
#define XTAL40M_RAMP_1G6_110US    ( 0x02530898 ) //  1.6G 110us
#define XTAL40M_RAMP_1G6_60US     ( 0x044404B0 ) //  1.6G 60us
#define XTAL40M_RAMP_1G6_30US     ( 0x08880258 ) //  1.6G 30us
#define XTAL40M_RAMP_1G6_30US_M   ( 0x80000000 | XTAL40M_RAMP_1G6_30US )    // -1.6G 30us


#if APPLICATION_MODE == APPLICATION_MODE_ROM_START
#define RAMP_GET(x) XTAL40M_##x
#elif APPLICATION_MODE == APPLICATION_MODE_XIP_START
#define RAMP_GET(x) XTAL20M_##x
//#define RAMP_GET(x) XTAL40M_##x
#else
#error xxxx
#endif


#if 1 /*ANA默认配置、ANA/DP控制字 */

/*cfg0 define*/
#define ANA1_XTAL_CAP (8)
#define ANA1_XTAL_DIS (0)
#define ANA1_VDD_DIS  (0)
#define ANA1_LRC_TUNE (1)
#define ANA1_PLL1_EN  (0)
#define ANA1_PLL2_EN  (0)
#define ANA1_ADC_EN   (0)
#define ANA1_ADC_CH1_EN   (0)
#define ANA1_ADC_CH0_EN   (0)
#define ANA1_LDO_IF_EN    (0)
#define ANA1_LDO_RF_EN    (0)

#define ANA1_PLL3_EN (0ul)
#define ANA1_HPF1 (2) /*0-100k 1-140k 2-200k 3-260k*/
#define ANA1_HPF2 (2) /*0-50k 1-100k 2/3-160k*/
#define ANA1_ANT2_RX_EN (0)
#define ANA1_ANT1_RX_EN (0)
#define ANA1_PGA1 (0) /*0~3*/
#define ANA1_PGA2 (0) /*0~3*/
#define ANA1_PGA3 (0) /*0~3*/

/*cfg2 define*/
#define ANA1_PA1_POWER (3)
#define ANA1_PA2_POWER (3)
#define ANA1_VDD12_DIS (0)

/*cfg0 define*/
#define ANA2_XTAL_CAP (8)
#define ANA2_XTAL_DIS (0)
#define ANA2_VDD_DIS  (0)
#define ANA2_LRC_TUNE (1)
#define ANA2_PLL1_EN  (1)
#define ANA2_PLL2_EN  (1)
#define ANA2_ADC_EN   (1)
#define ANA2_ADC_CH1_EN   (1)
#define ANA2_ADC_CH0_EN   (1)
#define ANA2_LDO_IF_EN    (1)
#define ANA2_LDO_RF_EN    (1)
/*cfg1 define*/
#define ANA2_PLL3_EN (1ul)
#define ANA2_HPF1 (3) /*0-100k 1-140k 2-200k 3-260k*/
#define ANA2_HPF2 (3) /*0-50k 1-100k 2/3-160k*/
#define ANA2_ANT2_RX_EN (1)
#define ANA2_ANT1_RX_EN (1)
#define ANA2_PGA1 (2) /*0~3*/
#define ANA2_PGA2 (2) /*0~3*/
#define ANA2_PGA3 (2) /*0~3*/
/*cfg2 define*/
#define ANA2_PA1_POWER (3)
#define ANA2_PA2_POWER (3)
#define ANA2_VDD12_DIS (0)

/*cfg0 define*/
#define ANA3_XTAL_CAP (8)
#define ANA3_XTAL_DIS (0)
#define ANA3_VDD_DIS  (0)
#define ANA3_LRC_TUNE (1)
#define ANA3_PLL1_EN  (1)
#define ANA3_PLL2_EN  (1)
#define ANA3_ADC_EN   (1)
#define ANA3_ADC_CH1_EN   (1)
#define ANA3_ADC_CH0_EN   (1)
#define ANA3_LDO_IF_EN    (0)
#define ANA3_LDO_RF_EN    (0)

#define ANA3_PLL3_EN (1ul)
#define ANA3_HPF1 (3) /*0-100k 1-140k 2-200k 3-260k*/
#define ANA3_HPF2 (3) /*0-50k 1-100k 2/3-160k*/
#define ANA3_ANT2_RX_EN (0)
#define ANA3_ANT1_RX_EN (0)
#define ANA3_PGA1 (2) /*0~3*/
#define ANA3_PGA2 (0) /*0~3*/
#define ANA3_PGA3 (0) /*0~3*/

/*cfg2 define*/
#define ANA3_PA1_POWER (3)
#define ANA3_PA2_POWER (3)
#define ANA3_VDD12_DIS (0)


/*cfg0 define*/
#define ANA4_XTAL_CAP (8)
#define ANA4_XTAL_DIS (1)
#define ANA4_VDD_DIS  (1)
#define ANA4_LRC_TUNE (1)
#define ANA4_PLL1_EN  (0)
#define ANA4_PLL2_EN  (0)
#define ANA4_ADC_EN   (0)
#define ANA4_ADC_CH1_EN   (0)
#define ANA4_ADC_CH0_EN   (0)
#define ANA4_LDO_IF_EN    (0)
#define ANA4_LDO_RF_EN    (0)

#define ANA4_PLL3_EN (0ul)
#define ANA4_HPF1 (2) /*0-100k 1-140k 2-200k 3-260k*/
#define ANA4_HPF2 (2) /*0-50k 1-100k 2/3-160k*/
#define ANA4_ANT2_RX_EN (0)
#define ANA4_ANT1_RX_EN (0)
#define ANA4_PGA1 (0) /*0~3*/
#define ANA4_PGA2 (0) /*0~3*/
#define ANA4_PGA3 (0) /*0~3*/

/*cfg2 define*/
#define ANA4_PA1_POWER (3)
#define ANA4_PA2_POWER (3)
#define ANA4_VDD12_DIS (1)

#endif

#define UDPCFG_ANA1_CFG0          ( ANA1_CFG0_DEFAULT | 0xC0 | (ANA1_XTAL_CAP<<20)|(ANA1_XTAL_DIS<<17)|(ANA1_VDD_DIS<<16)| (ANA1_LRC_TUNE<<14)|(ANA1_PLL1_EN<<13)|(ANA1_PLL2_EN<<12)|(ANA1_ADC_EN<<8)|(ANA1_ADC_CH1_EN<<3)|(ANA1_ADC_CH0_EN<<2)|(ANA1_LDO_IF_EN<<1)|ANA1_LDO_RF_EN)
#define UDPCFG_ANA1_CFG1          ( ANA1_CFG1_DEFAULT | (ANA1_PLL3_EN<<31)|(ANA1_HPF1<<14) | (ANA1_HPF2<<12) | (ANA1_ANT2_RX_EN<<9)|(ANA1_ANT1_RX_EN<<8)|(ANA1_PGA1<<4) | (ANA1_PGA2<<2) | ANA1_PGA3)
#define UDPCFG_ANA1_CFG2          ( ANA1_CFG2_DEFAULT | (ANA1_PA1_POWER<<26) | (ANA1_PA2_POWER<<19) | ANA1_VDD12_DIS)
												  
#define UDPCFG_ANA2_CFG0          ( ANA2_CFG0_DEFAULT | 0xC0 | (ANA2_XTAL_CAP<<20)|(ANA2_XTAL_DIS<<17)|(ANA2_VDD_DIS<<16)| (ANA2_LRC_TUNE<<14)|(ANA2_PLL1_EN<<13)|(ANA2_PLL2_EN<<12)|(ANA2_ADC_EN<<8)|(ANA2_ADC_CH1_EN<<3)|(ANA2_ADC_CH0_EN<<2)|(ANA2_LDO_IF_EN<<1)|ANA2_LDO_RF_EN)
#define UDPCFG_ANA2_CFG1          ( ANA2_CFG1_DEFAULT | (ANA2_PLL3_EN<<31)|(ANA2_HPF1<<14) | (ANA2_HPF2<<12) | (ANA2_ANT2_RX_EN<<9)|(ANA2_ANT1_RX_EN<<8)|(ANA2_PGA1<<4) | (ANA2_PGA2<<2) | ANA2_PGA3)
#define UDPCFG_ANA2_CFG2          ( ANA2_CFG2_DEFAULT | (ANA2_PA1_POWER<<26) | (ANA2_PA2_POWER<<19) | ANA2_VDD12_DIS)

// #define UDPCFG_ANA3_CFG0          ( ANA3_CFG0_DEFAULT | 0xC0 | (ANA3_XTAL_CAP<<20)|(ANA3_XTAL_DIS<<17)|(ANA3_VDD_DIS<<16)| (ANA3_LRC_TUNE<<14)|(ANA3_PLL1_EN<<13)|(ANA3_PLL2_EN<<12)|(ANA3_ADC_EN<<8)|(ANA3_ADC_CH1_EN<<3)|(ANA3_ADC_CH0_EN<<2)|(ANA3_LDO_IF_EN<<1)|ANA3_LDO_RF_EN)
// #define UDPCFG_ANA3_CFG1          ( ANA3_CFG1_DEFAULT | (ANA3_PLL3_EN<<31)|(ANA3_HPF1<<14) | (ANA3_HPF2<<12) | (ANA3_ANT2_RX_EN<<9)|(ANA3_ANT1_RX_EN<<8)|(ANA3_PGA1<<4) | (ANA3_PGA2<<2) | ANA3_PGA3)
// #define UDPCFG_ANA3_CFG2          ( ANA3_CFG2_DEFAULT | (ANA3_PA1_POWER<<26) | (ANA3_PA2_POWER<<19) | ANA3_VDD12_DIS)
// ANA3 采用ANA2配置 除ANA3_LDO_IF_EN、ANA3_LDO_RF_EN
#define UDPCFG_ANA3_CFG0          ( ANA2_CFG0_DEFAULT | 0xC0 | (ANA2_XTAL_CAP<<20)|(ANA2_XTAL_DIS<<17)|(ANA2_VDD_DIS<<16)| (ANA2_LRC_TUNE<<14)|(ANA2_PLL1_EN<<13)|(ANA2_PLL2_EN<<12)|(ANA2_ADC_EN<<8)|(ANA2_ADC_CH1_EN<<3)|(ANA2_ADC_CH0_EN<<2)|(ANA3_LDO_IF_EN<<1)|ANA3_LDO_RF_EN)
#define UDPCFG_ANA3_CFG1          ( ANA2_CFG1_DEFAULT | (ANA2_PLL3_EN<<31)|(ANA2_HPF1<<14) | (ANA2_HPF2<<12) | (ANA2_ANT2_RX_EN<<9)|(ANA2_ANT1_RX_EN<<8)|(ANA2_PGA1<<4) | (ANA2_PGA2<<2) | ANA2_PGA3)
#define UDPCFG_ANA3_CFG2          ( ANA2_CFG2_DEFAULT | (ANA2_PA1_POWER<<26) | (ANA2_PA2_POWER<<19) | ANA2_VDD12_DIS)

#define UDPCFG_ANA4_CFG0          ( ANA4_CFG0_DEFAULT | 0xC0 | (ANA4_XTAL_CAP<<20)|(ANA4_XTAL_DIS<<17)|(ANA4_VDD_DIS<<16)| (ANA4_LRC_TUNE<<14)|(ANA4_PLL1_EN<<13)|(ANA4_PLL2_EN<<12)|(ANA4_ADC_EN<<8)|(ANA4_ADC_CH1_EN<<3)|(ANA4_ADC_CH0_EN<<2)|(ANA4_LDO_IF_EN<<1)|ANA4_LDO_RF_EN)
#define UDPCFG_ANA4_CFG1          ( ANA4_CFG1_DEFAULT | (ANA4_PLL3_EN<<31)|(ANA4_HPF1<<14) | (ANA4_HPF2<<12) | (ANA4_ANT2_RX_EN<<9)|(ANA4_ANT1_RX_EN<<8)|(ANA4_PGA1<<4) | (ANA4_PGA2<<2) | ANA4_PGA3)
#define UDPCFG_ANA4_CFG2          ( ANA4_CFG2_DEFAULT | (ANA4_PA1_POWER<<26) | (ANA4_PA2_POWER<<19) | ANA4_VDD12_DIS)
																	  
#define UDPCFG_DP_CFG0            ( (UDFDEF_ANT_NUM - 1)<< 28 |(UDFDEF_RAMP_CNT - 1) << 20 | UDFDEF_ADCSAMP_NUMLOG      << 16 |	UDFDEF_ADCSAMP_OFFSET      << 8 |	 0 << 2 | 0 << 0)
#define UDPCFG_DP_CFG1            ( 0 << 8 | UDFDEF_CIC_SEC  << 4 | UDFDEF_DOWN_SEC << 0)
#define UDPCFG_DP_CFG2            ( (GET_OFFSET(UDFDEF_ADDR_ADCSAMP)/0x4000) << 24 |0 << 20 |0 << 16)
#endif


#if defined(UDF13_AT_BB_SRAM)
#if ANA4_VDD12_DIS > 0
#undef ANA4_VDD12_DIS
#define ANA4_VDD12_DIS (0)
#endif
#endif

#endif
